1. Technical Field
The present invention relates in general to an improved data processing system, and in particular to a method and system working with mixed instruction sets, e.g. 32 bit and 64 bit instructions within the data processing system. Still more particularly, the present invention relates to a method and system for renaming registers of said system as they are required for the concurrent execution of 32 bit and 64 bit instructions while having data dependencies among each other.
2. Description of the Related Art
As the quest for greater data processing system performance continues, central processing unit (CPU) designers have implemented superscalar data processing systems that are capable of issuing multiple independent instructions into multiple execution pipelines, wherein multiple instructions are executed in parallel. An example of such a superscalar data processing system is the superscalar microprocessor sold under the trademark "PowerPC" by IBM Microelectronics and Motorola Semiconductor. The "PowerPC" architecture is described in more detail in various user's manuals, including `PowerPC 603-RISC MICROPROCESSOR USER'S MANUAL," copyright 1994, IBM Part No. MPR6O3UMU-01.
Within the superscalar microprocessor, instructions are fetched from an instruction cache and are dispatched in program order to one of a plurality of execution units, wherein the instruction is executed by an execution unit appropriate for the particular type of instruction. For example, floating-point instructions are dispatched to one or more floating-point execution units, while fixed-point instructions are dispatched to one or more integer units. While instructions are dispatched in program order, instruction execution may occur out of order, depending upon availability of execution units and other data processing system resources.
In the superscalar processor, instructions may be dispatched, executed, and "finished" before other instructions that were previously dispatched. In order to prevent out-of-order instruction execution from placing data in an architected register at the wrong time, instruction execution is "completed" in program order by a completion unit. Thus, a subsequently dispatched instruction may "finish" before a previously dispatched instruction finishes, but the subsequently dispatched instruction may not be "completed" before completion of the previously dispatched instruction.
As is known in the art, "PowerPC" includes register renaming techniques for resolving data dependencies between instructions following each other after passing the dispatching unit. Logical registers are assigned to a plurality of physical registers in an assignment list so that they can be passed to a plurality of reservation stations each dedicated to supply a given execution unit with instructions to be executed.
With increasing need to address more than 4 Gigabyte of data--the maximum address space being addressable with 32 bit--the address calculation necessitates registers and arithmetic units capable to process address data with the next step size of 64 bit addresses. A special need exists, however, to handle both, 32 bit and 64 bit handling in structions--mixed instruction sets--in one program.
In general, 32 bit instructions leave the high part of a 64 bit register unchanged, succeeding 64 bit instructions use the full register size with the changes made by 32 bit instructions.
Register renaming as used for speculative instruction execution requires to write newly generated result data into a new physical register, thus ensuring that architected, logical registers can be kept in program order at retire time and to have a mean to discard faulty executed instructions.
The result data of the preceding 32 bit instructions cannot be used, because consecutive 32 bit LOAD instructions would get a source dependency on the preceding LOAD instruction. All 32 bit LOAD instructions would be executed in-order: each LOAD had to wait until the preceding one has processed its result data, required as source of the high part register contents in the succeeding instruction.
Straight forward 64 bit/32 bit register renaming would break a 64b register into a high and a low part register and would rename the both registers separately. But this approach would double the renaming logic with possible impact on the cycle time of the processor.